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? 2016 microchip technology inc. ds20005650a-page 1 pl613-01 features ? designed for pcb space savings with three low-power programmable plls and up to 8 clock outputs ? low power consumption - 10 a typical when pdb is activated ? output frequency: - 110 mhz at 1.8v operation - 166 mhz at 2.5v operation - 200 mhz at 3.3v operation ? input frequency: - fundamental crystal: 10 mhz to 40 mhz - reference input: 10 mhz to 200 mhz ? programmable i/o pins can be configured as output enable (oe), c onfiguration switching (csel), frequency switching (fselx), power down (pdb) inputs, or clock outputs ? disabled outputs programmable as hiz or active low ? four distinct configurations selectable with csel[0:1] ? single 1.8v, 2.5v, or 3.3v 10% power supply ? temperature range: 0c to 70c, ?40c to +85c ? available in 3 mm x 3 mm qfn or tssop packages general description the pl613-01 is an advanced triple pll design based on microchip?s picopll?, the world?s smallest programmable clock, technology. this advanced technology allows the eight output pl613-01 to fit in to a small 3 mm x 3 mm qfn or tssop package for high performance, low-power, low-cost applications. besides its small form factor and 8 outputs that can reduce overall system costs, the pl613-01 offers superior phase noise, jitter and power consumption performance. the power down feature of pl613-01, when activated, allows the ic to consume less than 10 a of power, while its csel[0:1] allows switching between up to four pre-programmed configurations. the fselx, on the other hand, allows frequency switching of two outputs (clk1 and clk2) on a single clock pin (clk2). block diagram pl613-01 programmable function xtal osc xout programmable pll1 xin/fin programmable pll3 clk4 odd/even divider (5-bits) clk5, oe6, csel0 clk6, oem, pdb clk7, oe0, csel1 vco1 vco3 clk0, fselx odd/even divider (5-bits) clk1, oe2 odd/even divider (5-bits) clk3, oe4 clk2 programmable pll2 vco2 fref fref 1, 2, 4, 8 odd/even divider (5-bits) odd/even divider (5-bits) fref fref programming interface output drive pdb fselx oe, oem 1, 2, 4, 8 1, 2, 4, 8 csel[0:1] 1.8v to 3.3v, picopll, 3-pl l, 200 mhz, 8 output clock ic
pl613-01 ds20005650a-page 2 ? 2016 microchip technology inc. 1.0 electrical characteristics absolute maximum ratings ? supply voltage range (v dd )..................................................................................................................... ?0.5v to +4.6v input voltage range (v in ) .................................................................................................................?0.5v to v dd + 0.5v output voltage range (v out ) ...........................................................................................................?0.5v to v dd + 0.5v data retention at +85c ........................................................................................................ ............................. 10 years ? notice: stresses above those listed under ?absolute maximu m ratings? may cause permanent damage to the device. this is a stress rating only and functiona l operation of the device at those or an y other conditions above those indicated in the operational sections of this s pecification is not intended. exposure to maximum rating conditions for extended periods may affect device reliability.
? 2016 microchip technology inc. ds20005650a-page 3 pl613-01 table 1-1: ac electrical characteristics parameters sym. min. ty p. max. units conditions crystal input frequency x in 10 ? 40 mhz fundamental crystal input frequency f in 10 ? 200 mhz at v dd = 3.3v, 10% 10 ? 166 mhz at v dd = 2.5v, 10% 10 ? 110 mhz at v dd = 1.8v, 10% input signal amplitude ? 0.8 ? v dd v pp internally ac-coupled output frequency ? 1?200mhz at v dd = 3.3v, 10% (high drive) 1?166mhz at v dd = 2.5v, 10% (high drive) 1?110mhz at v dd = 1.8v, 10% (high drive) settling time ? ? ? 2 ms at power-up (v dd 90% of operating v dd ) output enable time ? ??500ns oe function; t a = 25c, 15 pf load. add one clock period to this measurement for a usable clock output. ?? 2ms pdb function; t a = 25c, 15 pf load. v dd sensitivity ? ?2 ? 2 ppm frequency vs. v dd , 10% output rise time ? ? 1.2 1.7 ns 15 pf load, 10/90% v dd , high drive, 3.3v output fall time ? ? 1.2 1.7 ns 15 pf load, 10/90% v dd , high drive, 3.3v duty cycle ? 45 50 55 % pll-driven output, @ v dd /2, 15 pf load, high drive, over entire frequency range period jitter ( note 1 ) (10,000 samples) ??300?ps configuration-dependent, with capacitive decoupling between v dd and gnd note 1: jitter performance depends on the programming parameters. table 1-2: dc electrical characteristics parameters sym. min. typ. max. units conditions supply current (v dd = 3.3v) i dd ?1723ma all 8 outputs @ 20 mhz no load supply current (v dd = 2.5v) i dd ?13.518 ma all 8 outputs @ 20 mhz no load supply current (v dd = 1.8v) i dd ?9.513ma all 8 outputs @ 20 mhz no load supply current i dd ? 10 ? a when pdb = 0 operating voltage v dd 2.97 3.3 3.63 v configured for 3.3v operation 2.25 2.5 2.75 v configured for 2.5v operation 1.62 1.8 1.98 v configured for 1.8v operation output low voltage v ol ??0.4v i ol = +4 ma, standard drive, 3.3v
pl613-01 ds20005650a-page 4 ? 2016 microchip technology inc. output high voltage v oh 2.4 ? ? v i ol = ?4 ma, standard drive, 3.3v output current, low drive i old 4??mav ol = 0.4v, v oh = 2.4v, 3.3v output current, standard drive i osd 8??mav ol = 0.4v, v oh = 2.4v, 3.3v output current, high drive i ohd 16 ? ? ma v ol = 0.4v, v oh = 2.4v, 3.3v table 1-2: dc electrical characteristics (continued) parameters sym. min. typ. max. units conditions table 1-3: crystal characteristics parameters symbol min. typ. max. units fundamental crystal resonator frequency f xin 10 ? 40 mhz crystal loading rating c l(xtal) ?15?pf operating drive level ? ? 0.1 2 mw metal can crystal, shunt capacitance c0 ? ? 5.5 pf metal can crystal, esr max. esr ? ? 40 ? small smd crystal, shunt capacitance c0 ? ? 2.5 pf small smd crystal, esr max. esr ? ? 60 ? temperature specifications ( note 1 ) parameters sym. min. typ. max. units conditions temperature ranges storage temperature range t s ?65 ? +150 c ? soldering temperature ? ? ? +260 c ? ambient operating temperature range t a ?40 ? +85 c ? note 1: exposure of the device under condit ions beyond the limits specified by maximum ratings for extended periods may cause permanent damage to the device an d affect product reliability. these conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. operating temperature is guaranteed by design. parts are tested to commercial grade only.
? 2016 microchip technology inc. ds20005650a-page 5 pl613-01 2.0 pin descriptions the descriptions of the pins are listed in table 2-1 . package types note 1: ^ denotes internal pull-up. clk0, fselx^ vdd gnd clk1, oe2^ gnd xin, fin xout vdd clk5, oe6^, csel0 clk6, oem^, pdb^ vdd clk7, oe0^, csel1 clk4 clk3, oe4^ gnd clk2 1 2 3 4 56 78 12 11 10 9 16 15 14 13 1 xin, fin gnd clk5, oe6^, csel0 clk6, oem^, pdb^ vdd clk7, oe0^, csel1 clk0, fselx vdd 16 xout vdd clk4 clk3, oe4^ gnd clk2 clk1, oe2^ gnd 15 14 13 12 11 10 9 2 3 4 5 6 7 8 pl613-01 16-p in qfn (t op v iew ) pl613-01 16-p in tssop (t op v iew ) table 2-1: pin function table pin number qfn-16 pin number tssop-16 pin name pin type ( note 1 ) description 17 clk0, fselx b programmable clock (clk0) output or clk2 frequency switching (fselx) input. 3, 6, 12 2, 9, 12 gnd p ground connection. 2, 9, 15 5, 8, 15 vdd p v dd connection. 410 clk1, oe2 b programmable clock (clk1) output or output enable (oe) input for clk2. 5 11 clk2 o programmable clock (clk2) output. 713 clk3, oe4 b programmable clock (clk3) output or output enable (oe) input for clk4. 8 14 clk4 o programmable clock (clk4) output. 10 16 xout o crystal output pin. do not connect when using fin. 11 1 xin, fin i crystal or reference clock input. 13 3 clk5, oe6, csel0 b programmable clock (clk5) output or output enable (oe) input for clk6 or configuration switching input.
pl613-01 ds20005650a-page 6 ? 2016 microchip technology inc. 14 4 clk6, oem, pdb b programmable clock (clk6) output or output enable master (oem) all clock outputs or power down mode (pdb) input. 16 6 clk7, oe0, csel1 b programmable clock (clk7) output or output enable (oe) input for clk0 or configuration switching input. note 1: all bidirectional buffers (i/os) incorporate an internal 60 k ? pull-up resistor when used as an input, except when pdb mode is used. in configurations that use pdb, the pdb pin will have a 10 m ? pull-up resistor. table 2-2: key programming parameters clk[0:7] output frequency output drive strength programmable input/output clk[0,3,6]: f vcox / (p*(1,2,4,8)), f ref , or f ref / (p*(1,2,4,8)) clk[1,4,7]: f vcox / p clk[2,5]: f vcox / p, f ref , or f ref / p where f vcox = f ref * m / r m = 11 bit r = 8 bit p = 5 bit (odd/even divider) each output has three optional drive strengths to choose from: ?low: 4ma ? standard: 8 ma (default) ? high: 16 ma most pins are multi-function i/os. in addition to clk, they can be configured to perform as the following: ? oe[0,2,4,6]: output enable for individual i/os. ? oem: master oe controlling all outputs. ? csel[0:1]: device configuration switching. ? fselx: clk2 frequency switching. ? pdb: power down. ? clk[0:8]: output. ? hiz or active-low disabled state. table 2-1: pin function table (continued) pin number qfn-16 pin number tssop-16 pin name pin type ( note 1 ) description
? 2016 microchip technology inc. ds20005650a-page 7 pl613-01 3.0 functional description the pl613-01 is a highly featured, very flexible, advanced triple-pll design for high performance, low-power applications. the device accepts a low-cost fundamental crystal input of 10 mhz to 40 mhz or a reference clock input of 10 mhz to 200 mhz and is capable of producing eight distinct output frequencies up to 200 mhz. all three plls are fully programmable, with a total of five, 5- bit post-vco, odd/even ?p-counter? dividers with an additional 1, 2, 4, or 8 ?post p-counter? dividers that easily generate the most demanding frequencies. the outputs can be programmed to deliver t he generated frequencies from the plls or the reference input. each bidirectional feature pin (i/o) on the pl613-01 incorporates a 60 k ? pull-up resistor and can be configured to perform various functions. usage of various design features of these products is mentioned in the following paragraphs. 3.1 pll programming the three plls in pl613-01 are fully programmable. each pll is equipped with an 8-bit input frequency divider (r-counter) and an 11-bit vco frequency feedback loop (m-counter) divider. the three pll outputs are transferred to five 5-bit post-vco, odd/even dividers (p-counter), as shown in the block diagram . in addition, there are three optional (1, 2, 4, or 8) post p-counter dividers that can further divide the vco frequency. in general, the pll output frequency is determined by the following formula: equation 3-1: for output calculations, please note that ?p? includes the p-counter bits plus the additional optional dividers (1, 2, 4, or 8), if used. 3.2 clkx (clock outputs) there are a maximum of eight outputs available on the pl613-01. clock output fr equencies can be configured as follows: ? clk[0,3,6] -f vcox / (p*(1, 2, 4, 8)) -f ref (crystal or reference clock frequency) -f ref / (p*(1,2,4,8)) ? clk[1, 7] -f vcox / p ? clk[2, 4, 5] -f vcox / p -f ref -f ref / p each output can be programmed with a 4 ma, 8 ma, or 16 ma drive strength. the maximum output frequency is 200 mhz at 3.3v, 166 mhz at 2.5v, or 110 mhz at 1.8v. 3.3 oe (output enable) four pins can be configured as oe inputs for controlling individual clock outputs, as show in the table below. typical enable time is <500 ns plus one clock period. the oe feature can be prog rammed to allow the output to float (hiz) or to operate in active-low mode. the programming control for individual oes is show below. 3.4 oem (master output enable) one pin can be configured to be a single master oe (oem) input pin that contro ls all the outputs of the pl613-01. in addition, the st ate of the disabled outputs can be programmed to float (hiz) or to operate in active-low mode. the oem function operates on the following logic: typical enable time is <500 ns plus one clock period. f out f ref m ? ?? rp ? ?? ? = oex controls output on clk# oe0 clk0 oe2 clk2 oe4 clk4 oe6 clk6 oe pin oe type (programmable) osc pll output 0 0 (default) on on hiz 1onon active 0 1 normal operation (default) oe pin oe type (programmable) osc pll output 0 0 (default) on on hiz 1onon active 0 1 normal operation (default)
pl613-01 ds20005650a-page 8 ? 2016 microchip technology inc. 3.5 pdb (power down control) when activated, pdb disables all the plls, the oscillator circuitry, counters, and all other active circuitry. pdb activation disables all outputs and the ic consumes <10 a of power. the pdb input incorporates a 10 m ? pull-up resistor for normal operation. the pdb feature can be programmed to allow the output to float (hiz) or to operate in active-low mode. the logic for pdb is shown in the following table: typical enable time from power down in <2 ms. 3.6 csel (on-the-fly configuration switching) the pl613-01 can be programmed to allow switching between four different configurations, allowing for changes in the output frequ encies. many applications (i.e. video/audio) can use the same design footprint, but allow for configurati on switching, adhering to various standards. csel0 and csel1 are used in the switching selection. thes e pins incorporate a 60 k ? pull-up resistor for normal operation. the logic for configuration switching of the programmed parts is shown below: typical enable time is <500 s. 3.7 fselx (on-the-fly output frequency switching between two output frequencies) the pl613-01 is equipped with the fselx feature to allow frequency switching between two frequencies on one of the output pins. frequencies assigned to clk1 and clk2 can be switched when fselx is activated on clk2 output. the logic for fselx is shown below: typical enable time is <10 ns plus one clock period. pdb pin pdb type (programmable) osc pll output 0 0 (default) off off hiz 1offoff active 0 1 normal operation (default) csel1 csel0 programmed configuration 00 0 01 1 10 2 1 1 3 (default) fselx clk2 output 0 frequency 2 1 (default) frequency 1
? 2016 microchip technology inc. ds20005650a-page 9 pl613-01 4.0 layout recommendations the following guidelines are designed to help create a performance-optimized pcb design. 4.1 signal integrity and termination considerations ? keep traces short. ? trace = inductor. with capacitive loads, this creates ringing. ? long trace = long transmission line. without proper termination, this causes reflections that look like ringing. ? design long traces (greater than one inch) as striplines or microstrips with defined impedance. ? match trace at one side to avoid reflections bouncing back and forth. 4.2 decoupling and power supply considerations ? place decoupling capacitors as close as possible to the v dd pin(s) to limit noise from the power supply. ? multiple v dd pins should be decoupled separately for best performance. ? the addition of resistors in series with v dd can help prevent noise from other board sources. - traditionally, ferrite beads are used for this purpose, but with the pl613-01 the results are better when using resistors. figure 4-1: typical cmos termination. figure 4-2: crystal tuning circuit. 4.3 layout example figure 4-3: pl613-01 layout example. u1 = pl613-01 in qfn-16l. in this example, all eight outputs are used. c1a, c2a, c3a = 0.1 f and c1b, c2b, c3b = 1 f for power supply decoupling. the vias connected to the capacitors go to the ground plane inside the pcb. rp1, rp2, rp3 = 10 ? for power supply filtering. the power supply filter is a firs t order low pass filter with ?3 db at 30 khz. it is impor tant that the frequencies of the loop bandwidth of the plls are filtered properly. the loop bandwidth of the plls is in the range of 100 khz to 1 mhz depending upon the programmed configuration. the vias connected to rp1, rp2, and rp3 go to the v dd plane inside the pcb. r0 ~ r7 = 30 ? for matching clk0 ~ clk7 outputs to the pcb trace impedance. place the resistors as close as possible to the ic pins and design the traces to the typical cmos termination place series resistor as close as possible to cmos output. cmos output buffer 7\slfdoexiihulpshgdqfh to cmos input series resistor use value to match output buffer impedance wr wudfh7\slfdoydoxhlv /lqh crystal tuning circuit series and parallel capacitors used to fine tune the crystal load to the circuit load. crystal xin 18 xout cpt cpt cst cst: series capacitor that is used to lower circuit load to match crystal load. raises frequency offset. this can be eliminated by using a crystal with a c load of equal or greater value than the oscillator. cpt: parallel capacitors that are used to raise the circuit load to match the crystal load. lowers frequency offset. clk4 clk3 clk2 clk5 clk6 clk7 clk0 clk1
pl613-01 ds20005650a-page 10 ? 2016 microchip technology inc. target clock inputs as transmission lines (microstrip or stripline) for the best signal integrity and the lowest emi. when using ferrite beads instead of rp1, rp2, or rp3, make sure the resonance frequency of the bead with the decoupling capacitors is below 50 khz so as not to interfere with the pll loop bandwidth. this requirement is difficult to fulfill, so it is recommended to use the resistors rp1, rp2, and rp3 for power supply filtering.
? 2016 microchip technology inc. ds20005650a-page 11 pl613-01 5.0 packaging information 5.1 package marking information 16-pin qfn* xxxxxx nnn xxx 16-pin tssop* example p613-01 13016 a20 xxxx-xx wwnnn xxx example p61301 420 k79 legend xx...x product code or cust omer-specific information y year code (last digit of calendar year) yy year code (last 2 digits of calendar year) ww week code (week of january 1 is week ?01?) nnn alphanumeric traceability code pb-free jedec ? designator for matte tin (sn) * this package is pb-free. the pb -free jedec designator ( ) can be found on the outer packaging for this package. , , pin one index is identified by a dot, delta up, or delta down (triangle mark). note : in the event the full microchip part numbe r cannot be marked on one line, it will be carried over to the next line, t hus limiting the number of available characters for customer-specific informa tion. package may or may not include the corporate logo. underbar (_) and/or overbar ( ? ) symbol may not be to scale. 3 e 3 e
pl613-01 ds20005650a-page 12 ? 2016 microchip technology inc. 16-lead qfn package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging.
? 2016 microchip technology inc. ds20005650a-page 13 pl613-01 16-lead tssop package outline and recommended land pattern note: for the most current package drawings, please see the microchip packaging specification located at http://www.microchip.com/packaging.
pl613-01 ds20005650a-page 14 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005650a-page 15 pl613-01 appendix a: revision history revision a (october 2016) ? converted micrel document pl613-01 to micro- chip data sheet ds20005650a. ? minor text changes throughout. ? discontinued ssop package offering.
pl613-01 ds20005650a-page 16 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005650a-page 17 pl613-01 product identification system to order or obtain information, e.g., on pricing or delivery, contact your local microchip representative or sales office . part no. x temperature device device: pl613-01: 1.8v to 3.3v, picopll, 3-pll, 200 mhz, 8 output clock ic id code: xxx = unique 3-digit code assigned at programming time package: o = 16-lead tssop q = 16-lead qfn temperature: c = 0c to +70c (commercial) i = ?40c to +85c (industrial) media type: blank= tube tr = tape & reel xxx id code x package xx media type examples: a) pl613-01-xxxoc: 1.8v to 3.3v, picopll, 3-pll, 200 mhz, 8 output clock ic 3-digit id code, 16-lead tssop, commercial temperature range, tube b) PL613-01-XXXOI-TR: 1.8v to 3.3v, picopll, 3-pll, 200 mhz, 8 output clock ic 3-digit id code, 16-lead tssop, industrial temperature range, tape & reel c) pl613-01-xxxqc-tr: 1.8v to 3.3v, picopll, 3-pll, 200 mhz, 8 output clock ic 3-digit id code, 16-lead qfn, commercial temperature range, tape & reel d) pl613-01-xxxqi: 1.8v to 3.3v, picopll, 3-pll, 200 mhz, 8 output clock ic 3-digit id code, 16-lead qfn, industrial temperature range, tube e) pl613-01-xxxoc-tr: 1.8v to 3.3v, picopll, 3-pll, 200 mhz, 8 output clock ic 3-digit id code, 16-lead tssop, commercial temperature range, tape & reel
pl613-01 ds20005650a-page 18 ? 2016 microchip technology inc. notes:
? 2016 microchip technology inc. ds20005650a-page 19 information contained in this publication regarding device applications and the like is prov ided only for your convenience and may be superseded by updates. it is your responsibility to ensure that your application me ets with your specifications. microchip makes no representations or warranties of any kind whether express or implied, written or oral, statutory or otherwise, related to the information, including but not limited to its condition, quality, performance, merchantability or fitness for purpose . microchip disclaims all liability arising from this information and its use. use of microchip devices in life support and/or safe ty applications is entirely at the buyer?s risk, and the buyer agrees to defend, indemnify and hold harmless microchip from any and all damages, claims, suits, or expenses resulting fr om such use. no licenses are conveyed, implicitly or ot herwise, under any microchip intellectual property rights unless otherwise stated. trademarks the microchip name and logo, the microchip logo, anyrate, dspic, flashflex, flexpwr, heldo, jukeblox, keeloq, keeloq logo, kleer, lancheck, link md, medialb, most, most logo, mplab, optolyzer, pic, picstart, pic32 logo, righttouch, spynic, sst, sst logo, superflash and uni/o are registered trademarks of microchip technology incorporated in the u.s.a. and other countries. clockworks, the embedded control solutions company, ethersynch, hyper speed control, hyperlight load, intellimos, mtouch, precision edge, and quiet-wire are registered trademarks of microc hip technology incorporated in the u.s.a. analog-for-the-digital age, any capacitor, anyin, anyout, bodycom, chipkit, chipkit logo, codeguard, dspicdem, dspicdem.net, dynamic average matching, dam, ecan, ethergreen, in-circuit serial programming, icsp, inter-chip connectivity, jitterblocker, kleernet, kleernet logo, miwi, motorbench, mpasm, mpf, mplab certified logo, mplib, mplink, multitrak, netdetach, omniscient code generation, picdem, picdem.net, pickit, pictail, puresilicon, righttouch logo, real ice, ripple blocker, serial quad i/o, sqi, superswitcher, superswitcher ii, total endurance, tsharc, usbcheck, varisense, viewspan, wiperlock, wireless dna, and zena are trademarks of microchip technology incorporated in the u.s.a. and other countries. sqtp is a service mark of mi crochip technology incorporated in the u.s.a. silicon storage technology is a registered trademark of microchip technology inc. in other countries. gestic is a registered tradem arks of microchip technology germany ii gmbh & co. kg, a subsidiary of microchip technology inc., in other countries. all other trademarks mentioned herein are property of their respective companies. ? 2016, microchip technology incorporated, printed in the u.s.a., all rights reserved. isbn: 978-1-5224-1038-6 note the following details of the code protection feature on microchip devices: ? microchip products meet the specification cont ained in their particular microchip data sheet. ? microchip believes that its family of products is one of the mo st secure families of its kind on the market today, when used i n the intended manner and under normal conditions. ? there are dishonest and possibly illegal meth ods used to breach the code protection fe ature. all of these methods, to our knowledge, require using the microchip pr oducts in a manner outside the operating specif ications contained in microchip?s data sheets. most likely, the person doing so is engaged in theft of intellectual property. ? microchip is willing to work with the customer who is concerned about the integrity of their code. ? neither microchip nor any other semiconduc tor manufacturer can guarantee the security of their code. code protection does not mean that we are guaranteeing the product as ?unbreakable.? code protection is constantly evolving. we at microchip are committed to continuously improving the code protection features of our products. attempts to break microchip?s c ode protection feature may be a violation of the digital millennium copyright act. if such acts allow unauthorized access to your softwa re or other copyrighted work, you may have a right to sue for relief under that act. microchip received iso/ts-16949:2009 certification for its worldwide headquarters, design and wafer fabrication facilities in chandler and tempe, arizona; gresham, oregon and design centers in california and india. the company?s quality system processes and procedures are for its pic ? mcus and dspic ? dscs, k ee l oq ? code hopping devices, serial eeproms, microper ipherals, nonvolatile memory and analog products. in addition, microchip?s quality system for the design and manufacture of development systems is iso 9001:2000 certified. quality management s ystem by dnv == iso/ts 16949 ==
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